Regviz

Allwinner /D1H /UART[3] /RFL

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Interpret as RFL

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https://regviz.com/r/Allwinner/D1H/UART[3]/RFL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0rfl

Description

UART Receive FIFO Level Register

Fields

rfl

RX FIFO Level

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data